Synchronous Up/down Counter with Period Independent of Counter Size

1 Synchronous Up/Down Counter with Period Independent of Counter Size Mircea R. Stan, Wayne P. Burleson [email protected] Abstract| The theory and practice of up-only (or downonly) prescaled counters is well understood both in industry and in the academia but until now it was not known if the design of a prescaled up/down binary counter is possible. This paper presents the theory behind building such a synchronous up/down counter of arbitrary length and with period independent of counter size by describing the design of a 64-bit up/down counter running at 40MHz implemented in an AtmelAT6000 SRAM-based FPGA. The main idea behind the novel up/down counter design is to recognize that the only extra di culty with an up/down (vs. an up-only or down-only) constant time counter is when the counter changes \state" from counting up to counting down and vice-versa. For dealing with this di culty the new design uses a \shadow" register that is always kept loaded with the previous counter value. When counting only up or only down the counter functions like a normal up-only or downonly prescaled counter but when it changes \state" from up to down or from down to up instead of trying to compute the new counter value and having to wait for carry propagation it simply swaps with the shadow register which contains the desired previous value. An Atmel AT6000 (former Concurrent Logic CLi6000 family) FPGA was used in this design but similar up/down counters can be implemented in any other technology or FPGA family. Keywords| Prescaled counter, constant time counter, up/down counter.